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19 - 6460; rev 0; 11/12 maxim integrated 1 some revisions of this device may incorporate deviations from published specifications known as errata. multiple revisions of any device may be simultaneously available through various sales channels. for information about device errata, go to: www.maximintegrated.com/errata . for pricing, delivery, and ordering information, please contact maxim direct at 1 - 888 - 629 - 4642, or visit maxims website at www.maximintegrated.com . MAX24001 2.5gbps tx burst - mode laser tran sceiver general description the MAX24001 is a complete burst - mode laser driver transmitter and limiting amplifier receiver for use within fiber optic modules for fttx applications. a fully compliant gpon/gepon module with digital diagnostics can be reali z ed when used with a 2 kb eeprom and suitable optics. alternatively, a microcontroller can be used in conjunction with the MAX24001 ; however, this is not a necessity in order to achieve sff - 8472 compliance. the 2.5gbps limiting receive path features programmable output s wing control, rate selection, and oma - based loss - of - signal detection. functions are also provided which facilitate the implementation of apd biasing without the need for an external dc - dc converter. the burst - mode laser driver has temperature compensated m odulation control using a lookup table. closed - loop control of laser power incorporates tracking error compensation and has multiple options for rapidly settling the laser power thus enabling fast registration and shutdown on the network. diagnostics are e nhanced with the inclusion of programmable transmit signal detection during bursts, and rogue onu detection between bursts. this is linked to a laser safety system which allows the modulation and bias currents to be shut off in response to a range of diffe rent fault conditions detected on - chip. the transmit and receive systems are independently powered and can respond separately to the sleep pin. the MAX24001 is highly configurable from either e eprom or low - cost mcu using a two - wire interface. applications gpon, gepon, gigabit ethernet f unctional diagram features ? 2.5gbps limiting receiver ? int egrated apd bias loop with overvoltage and overcurrent protection ? oma - b ased los d etection ? 1.25 gbps to 2.5gbps laser d river ? cml, lvpecl, hstl, sstl - compatible i nputs ? open and closed - loop bias control ? temperature - compensated i mod c ontrol ? highly configurable laser safety system ? transmit tx_sd and r ogue onu d etection ? sfp msa and sff - 8472 digital diagnostics ? integrated temperature sensor ? power - s aving sleep m odes ? exte rnal dac, a dc , and pwm i nterfaces ordering information part temp range pin - package MAX24001 tl + - 40 ? c to +95 ? c 40 t qfn - ep * + denotes a lead (pb) - free /rohs - compliant package. * ep = exposed p ad . r x _ o u t + r x _ o u t - r x _ i n + r x _ i n - l o s / s d 2 . 5 g b p s l i m i t i n g r e c e i v e r t x _ i n + t x _ i n - t x _ o u t + t x _ o u t - a d c t x _ f a u l t / d a c b e n + b e n - b i a s m p d t x _ s d / t x _ f a u l t s c l _ s l a v e s d a _ s l a v e s d a _ m a s t e r s c l _ m a s t e r r s s i s l e e p 2 . 5 g b p s b u r s t m o d e l a s e r d r i v e r a p d _ c t r l t x _ d i s a b l e t s e n s e t s e n s e _ r e t
maxim integrated 2 absolute maximum ratings voltage range on v dd_tx , v dd_ txo , v dd_rx , v dd_rxo ................................ ................................ ........... - 0.3v to +3.65v voltage range on any pin not otherwise specified (with respect to v ss_ * ) ........................... - 0.5v to ( v dd_ * + 0.5v ) continuous power dissipation (t a = +70 c ) tqfn (derate 35.7 mw/ c above +70 c ) ................................ ................................ ................................ . 2857.1mw operating temperature range ................................ ................................ ................................ ............ - 40 c to +95 c junction temperature ................................ ................................ ................................ ................................ ...... +150 c storage temperature ................................ ................................ ................................ ......................... - 70 c to +150 c lead temperature (soldering 10s) ................................ ................................ ................................ .................. +300 c soldering temperature (reflow) ................................ ................................ ................................ ....................... +260 c stresses beyond those listed under absolute ma ximum ratings may cause permanent damage to the device. these are stress ratings only, and functional opera - tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposu re to absolute maximum rating conditions for extended periods may affect device reliability. recommended dc operating conditions parameter symbol conditions min typ max units operating s upply v oltage v dd 3.0 3.3 3.6 v rssi pin compliance rosa sourcing to rssi pin v dd - 0.75 v rosa sinking from rssi pin 0.75 v bias pin c ompliance 0.8 v tx_out pin c ompliance 0.8 v mpd input current for correct apc loop operation 40 2000 a mpd input capacitance for correct apc loop operation 4 20 pf junction temperature - 40 + 120 c case t emperature - 40 + 95 c device not guaranteed to meet parametric specifications when operated beyond these conditions . permanent damage may be incurred by operating beyond these limits. electrical characteristics ( v cc = 2.97v t o 3.63v, t a = - 40c to +95c. ) (note 1) note 1 : electrical specifications are productio n tested at t a = +25c. specifications over the entire operating temperature range are guaranteed by design and characterization. typical specifications are at t a = +25c , 3.3v . continuous ratings parameter symbol conditions min typ max units supply c urrent idd excluding laser bias and modulation currents, 20ma bias and modulation current , rx cml output 40 0mv p - p 1 36 ma
maxim integrated 3 receiver characteristics parameter symbol conditions min typ max units differential input impedance 80 100 120 ? maximum input data rate 2.5 gbps minimum input data rate 1.25 gbps i nput s ensitivity differential, ber = 1e - 10, 2.5gbps, prbs 2 23 - 1 pattern 6.5 1 3 mv p - p deterministic jitter 2.5gbps, v out = 800 mv p - p , v in between 25 mv p - p differential and 1000 mv p - p 40 p s p - p random jitter 2.5gbps, v out = 800 mv p - p , v in between 25 mv p - p differential and 1000 mv p - p 2.7 ps rms output rise/fall t imes 2.5gbps, v out = 800 mv p - p , v in = 25mv p - p differential and 1000 mv p - p 60 ps low - frequency cut off 30 khz output i mpedance 1mhz d ifferential 80 100 120 ? minimum o utput s wing differen tial, 4 - bit programmable (note 2 ) 200 24 0 mv p - p maximum output swing differen tial, 4 - bit programmable (note 2 ) 800 880 mv p - p note 2 : measure d wi th 1111111100000000 pattern . loss of signal and rssi characteristics parameter symbol conditions min typ max units maximum oma los assert t ime 11 s maximum oma los deassert t ime 11 s maximum los threshold s etting 400 mv p - p los assert/deassert level los dac = 50 (note 3) 67 mv p - p los dac = 105 (note 3) 143 mv p - p maximum rssi c urrent l evel sourced or sunk from rssi pin 1200 a note 3 : los assert and deassert levels can be set independently to define hysteresis.
maxim integrated 4 transmitter characteristics parameter symbol conditions min typ max units maximum input data r ate prbs23 2. 488 gbps minimum input data r ate prbs23 1. 25 gbps maximum modulation c urrent 80 ma p - p minimum modulation c urrent 8 ma p - p maximum electrical rise/fall t ime (20% to 80%) measured using 15? effective termination, i mod = 8 ma p - p to 80 ma p - p 96 p s total jitter prbs1 5, 2.488gbps, i mod = 8 ma p - p to 8 0 ma p - p , differential electrical measurement 65 175 mui p - p deterministic jitter prbs15, 2.488gbps, i mod = 8 ma p - p to 80 ma p - p , diff erential electrical measurement 45 mui p - p random jitter prbs15, 2.488gbps, i mod = 8 ma p - p to 80 ma p - p , diff erential electrical measurement 1. 11 mui rms m aximum b ias c urrent 90 ma burst timings parameter symbol conditions min typ max units burst enable/disable time (electrical) disable: bias current reduced to 20% of its maximum value. enable: bias current increased to 90% of desired bias plus modulation current target bias current > 3ma 7 12 ns minimum burst length to u pdate apc l oop during closed - loop operation 90 ns minimum burst gap during closed - loop operation 75 ns ? maximum initial mean power control settling time (apc l oop) from power - on , negation of tx_disable, or negation of sleep to 90% of desired optical power . fast settling algorithm enabled , no fast start lut. bias c urrent o vershoot < 10% bias current > 4ma 1.2 ? s
maxim integrated 5 transmitter input characteristics typical i/o ranges for tx_in and ben are shown. tx_in and ben inputs are also compat ible with hstl and sstl for low - voltage operation . digital i/o characteristics parameter symbol conditions min typ max units time to initialise from power - up or hot plug 71 ms tx_disable a ssert tx_ disable assert to optical disable 0.3 s tx_disable n egate tx_ disable negate to optical enable 0.5 ms tx_disable to r eset time tx_disable must be held high to reset tx_ fault 0.155 s maximum d elay ben change to tx_sd r esponse rising or falling edge 100 ns light during gap to laser shutdown rogue onu 100 s typical i/o r anges for sleep, tx_disable, los and tx_sd v v i h i l v d d + 0 . 1 v d d - 2 . 0 c m l 3 v 3 v p p ( d i f f ) 0 . 2 v 1 . 6 v t x _ i n ( d i f f e r e n t i a l a c o r d c c o u p l e d ) b e n ( d i f f e r e n t i a l d c c o u p l e d ) i n p u t v o l t a g e r a n g e v i l ( m a x ) l v p e c l 3 v 3 v d d - 1 . 8 1 v d d - 1 . 4 8 v d d - 1 . 1 6 v d d - 0 . 8 8 v i l ( m i n ) v i h ( m a x ) v i h ( m i n ) t x _ i n ( d i f f e r e n t i a l a c o r d c c o u p l e d ) b e n ( d i f f e r e n t i a l d c c o u p l e d ) l v c m o s / l v t t l 3 v 3 v i l ( m a x ) - 0 . 3 0 . 8 v 2 v v d d v i l ( m i n ) v i h ( m a x ) v i h ( m i n ) t x _ i n ( d i f f e r e n t i a l a c o r d c c o u p l e d ) b e n ( d i f f e r e n t i a l d c c o u p l e d ) l o w s p e e d l v t t l 3 v 3 v i l ( m a x ) v s s 0 . 8 v 2 v v d d v i l ( m i n ) v i h ( m a x ) v i h ( m i n ) s l e e p , t x _ d i s a b l e i n p u t s l o w s p e e d l v t t l 3 v 3 v i l ( m a x ) v s s 0 . 4 v v d d v i l ( m i n ) v i h ( m a x ) v i h ( m i n ) l o s , t x _ s d o u t p u t s v d d - 0 . 5 v
maxim integrated 6 peripheral functions parameter symbol conditions min typ max units power - on - reset (p o r) v oltage module 3v3 supply voltage above which reset will not be asserted 2. 5 v module 3v3 supply voltage below which reset is guaranteed 2.2 v apd control parameter symbol conditions min typ max units adc pin minimum voltage 1. 30 v adc pin maximum voltage 2. 25 v dac pin minimum current 0 ma dac pin maximum current 0.45 ma dac pin compliance 1.5 v pwm frequency minimum pwm frequency 250 khz maximum pwm frequency 2 mhz step response settling time load current change from 20a to 1ma 2 ms sleep parameter symbol conditions min typ max units sleep assert/d eassert time to allow first operation or enter sleep from deassertion of sleep pin 100 n s
maxim integrated 7 two - wire interface characteristics parameter symbol conditions min typ max units maximum scl clock frequency 400 khz minimum scl c lock low p eriod t low 1200 ns minimum scl c lock high p eriod t high 600 ns minimum setup time for a repeated start c ondition t su:sta 600 ns minimum hold time (repeated ) start c ondition t hd:sta 600 ns minimum data hold time t hd:dat 0 ns minimum data setup time t su:dat 100 ns minimum setup time for stop c ondition t su:sto 600 ns minimum bus free time between a stop and start c ondition t buf 1200 ns maximum rise and f all times of both sda and scl s ignals t r, t f 300 ns minimum rise and fall times of both sda and scl s ignals t r, t f c b = capacitance of a single bus line c x = 20 + 0.1 x cb cx ns maximum c apacitance for each i/o p in 10 pf t h d : s t a t s u : s t a t h i g h t l o w t s u : d a t t h d : d a t t r t f t s u : s t o t b u f s d a s c l
maxim integrated 8 digital diagnost i cs parameter symbol conditions min typ max units temperature r eporting r esolution - 40 c to +95 c range 0.85 c / lsb maximum ina ccuracy single - point calibration , external mode 2 c power supply r eporting r esolution 3.0v to 3.6v range 10 mv/ lsb maximum ina ccuracy calibrated , within the supply reporting range 3 % tx bias r eporting r esolution 5ma to 90ma range 0.392 ma/ lsb maximum ina ccuracy calibrated , within the tx bias reporting range 10 % tx power mpd current reporting resolution mpd_range = 00 , 40a to 200 a 0.78 a/ lsb mpd_range = 01 , 100a to 800a 3.125 a/ lsb mpd_range = 10 , 400a to 2000a 12.5 a/ lsb maximum ina ccuracy calibrated, within the mpd operating range 20 % rx power rssi current reporting resolution 0 to 16 a (note 4 ) 0.5 a/ lsb 16 a to 206 a (note 4 ) 2.0 a/ lsb 206 a to 1000 a (note 4 ) 8.0 a/ lsb maximum inaccuracy 3 a to 25a, c alibrated ( n ote 4) 25 % 25a to 1000a, c alibrated ( n ote 4) 10 % note 4 : rx_rssi_scale = 00 (x1 gain) range and resolution settings can be changed to improve accuracy.
maxim integrated 9 pin configuration sleep los / sd v dd _ rxo rx _ out + rx _ out - v ss _ rxo sda _ slave scl _ slave sda _ master d a c / t x _ f a u l t tx _ sd / tx _ fault a p d _ c t r l v s s _ r x r x _ i n + r x _ i n - v d d _ r x r s s i r r e f v dd _ dig v s s _ d i g v ss _ txo tx _ out - tx _ out + v dd _ txo bias mpd t x _ d i s a b l e scl _ master t s e n s e _ r e t t s e n s e v d d _ t x t x _ i n + t x _ i n - v s s _ t x b e n - b e n + a d c v ss _ txo v s s _ r x v ss _ rxo 1 ep max 24001 top view 1 2 3 4 5 6 7 8 9 10 12 11 13 14 15 16 17 18 19 20 30 29 28 27 26 25 23 22 21 24 39 40 38 37 36 35 34 33 32 31 t qfn ( 5 mm x 5 mm )
maxim integrated 10 pin description pin name dir type function 1 scl_master o/p lvttl two - wire interface clock connection to eeprom , with internal 10k? pullup resistor 2 sda_master i/o lvttl two - wire interface data connection to eeprom , with internal 10k? pullup resistor 3 v dd_rxo analog +3.3v receiver output power supply 4 v ss_rxo analog gnd receiver output ground connection 5 rx_out - o/p cml limiting receiver inverted output . 50? to v dd_rxo 6 rx_out+ o/p cml limiting receiver noninverted output . 50? to v dd_rxo 7 v ss_rxo analog gnd receiver output ground connection 8 los/sd o/p lvttl loss - of - signal indication. o pen drain with external 4.7k? to 10k? resistor. 9 scl_slave i/p lvttl two - wire interface clock connection to host. with external 10k? pull up resistor 10 sda_slave i/o lvttl two - wire interface data connection to host. with external 10k? pull up resistor 11 tx_disable i/p lvttl internally pulled high to v dd_tx with a 7.5k? resistor 12 tsense analog analog temperature sensor current force 13 tsense_ret analog analog temperature sensor current return 14 v dd_tx analog +3.3v transmitter power supply 15 tx_in - i/p high speed transmitter input signal inverted 16 tx_in+ i/p high speed transmitter input signal noninverted 17 v ss_tx analog gnd transmitter ground connection 18 ben+ i/p high speed burst - enable noninverted 19 ben - i/p high speed burst - enable inverted 20 rref analog analog connects to external precision resistor 21 tx_sd / tx_fault o/p lvttl push - pull signal detect indication . can be configured as open - drain tx_fault output, pulled high externally using a 4.7k? to 10k? resistor. 22 mpd i/p analog monitor photodiode input 23 bias analog analog bias current sink 24 v ss_txo analog gnd transmitter output ground connection 25 tx_out+ o/p high speed laser data differential drive output 26 tx_out - o/p high speed laser data differential drive output 27 v ss_txo analog gnd transmitter output ground connection 28 v dd_txo analog +3.3v transmitter output power supply 29 sleep i/p lvttl sleep mode select 30 v dd_dig analog +3.3v digital power supply 31 v ss_dig analog gnd digital ground connection 32 rssi i/p analog rx photodiode m onitor (rssi) 33 v dd_rx analog +3.3v receiver power supply 34 v ss_rx analog gnd receiver ground connection 35 rx_in - i/p cml receiver input signal . differential 100? with rx_in+ . 36 rx_in+ i/p cml receiver input signal . differential 100? with rx_in - . 37 v ss_rx analog gnd receiver ground connection 38 adc i/p analog voltage input to on - chip adc 39 dac / tx_fault o/p analog current output for apd loop control . can be configured as open - drain tx_fault output, pulled high externally using a 4.7k? to 10k? resistor. 40 apd_ctrl o/p lvttl open - drain 1v2 or 3v3 o utput. externally pulled to power or ground depending on the application. ep analog gnd exposed p ad. solder to board to provide effective thermal connection to circuit board
maxim integrated 11 detailed description figure 1 . MAX24001 block diagram c m l r x _ o u t + r x _ o u t - r x _ i n + r x _ i n - i / p b u f f f i l t e r l i m i t p r e - e m p l o s / s d l o s d a c 2 . 5 g b p s l i m i t i n g r e c e i v e r v c m 5 0 r 5 0 r r a t e i n v e r t t x _ i n + t x _ i n - d r i v e p r e t x _ o u t + t x _ o u t - i n v e r t p w a d j u s t a d c d a c b e n + b e n - b e n a p d d a c s w i n g t h r e s h o l d 0 v v d d 0 v v d d i / p i n t e r f a c e 0 v v d d 0 v v d d i / p i n t e r f a c e d e - b o u n c e b i a s g a i n d r i v e b i a s d a c a p c l o o p c o n t r o l m o d d a c m i r r o r p o w e r m o n i t o r m p d t x s i g n a l d e t e c t l a s e r s a f e t y t x _ s d / t x _ f a u l t m o d u l a t i o n c o n t r o l m o d u l a t i o n s h u t d o w n f a u l t / 1 , / 4 , / 1 6 / 1 s c l _ s l a v e s d a _ s l a v e s d a _ m a s t e r s c l _ m a s t e r r e g i s t e r s a n d m e m o r y h o s t i n t e r f a c e r s s i s l e e p 2 . 5 g b p s b u r s t m o d e l a s e r d r i v e r a p d _ c t r l d i a g n o s t i c s a n d s f f - 8 4 7 2 a p d c o n t r o l t x _ d i s a b l e t s e n s e t s e n s e _ r e t t e m p s e n s o r t a r g e t p o w e r i n v e r t a p d b i a s s i n k / s o u r c e d i a g t r a c k i n g _ a d j u s t
maxim integrated 12 receiver signal path [control r egist er address r ange a4h: 90h to 93h ] the signal arriving at rx_in is terminated with a 100? load to minimise return loss. an input buffer adds peaking to compensate for up to 10mm of fr4. the level of peaking is controlled by the rx_input_peak register. the signal can also be inverted using rx_invert . rx_ratesel0 or rx_ratesel1 bandwidth (ghz) bit rate (gbps ) 00 1 1.25 01 1.8 2.488 the received signal is then band limited to one of two rates selected by the soft_rate_select bit of the system _control register (a2h: 7bh). if soft_rate_select = 0 then select rx_ratesel 0 else select rx_ratesel 1 . filter bandwidths are nominally designed to be 0.7x the available data rates. the cml output stage is a high - current driver that delivers a 2 00mv to 880mv signal from a low - impedance 50? output. the rx_output_swing register is used to control the signal at rx_out with 45mv resolution. pre - emphasis may also be applied to the output signal using rx_preemphasis . the pre - emphasis (defined as ((b - a)/b) x 100) can be set to 0%, 2%, 6% or 10% . the pre - emphasis ratio remains relatively constant when a is adjusted. figure 2 . rx pre - emphasis control the cml, pre - emphasis and limiting stages may be automatically powered down under loss - of - signal conditions (los = 1 ) by setting the los_squelch register. this feature uses the debounced los signal prior to any inversion caused by setting los_invert . alternatively, the cml, pre - emphasis and limiting stages may be directly powered down by setting the squelch register. re ceiver loss of signal (los) [contro l register address range a4h: 9bh to 9dh ] figure 3 . los detection system a b l o s _ a s s e r t l o s _ d e a s s e r t 0 1 d a c d e b o u n c e l o s r x _ i n + - l o s _ r a w p e a k d e t e c t l o s _ i n v e r t l o s _ i n h i b i t
maxim integrated 13 when the peak signal amplitude detected at rx_in drops below the threshold level set by los_assert then a loss - of - signal condition is reported on the los pin and the los_deassert threshold is selected. the signal amplitude must then rise back above the threshold set by los_deassert before the loss - of - signal condition is removed and the los_assert threshold is re - selected. the two thresholds can be used to introduce a wide range of hysteresis into los detection. the deassert threshold level should be higher than the assert threshold for correct operation. when the comparator output ( los_raw ) changes, the los deb ounce circuit holds the new value at its output for a programmable period of time controlled by los_debounce . longer debounce timeout periods may be required to accommodate the much longer timeframe pulses caused by the response of the tia agc when the sig nal is suddenly interrupted. the decay of the differential signal is characterized by an unwanted signal crossover as shown in the diagram below. the unwanted pulse on los_raw is rejected by setting the debounce period to > 50 s. figure 4 . los debounce operation the los_invert register is used to configure the pin for sign al detect (sd) instead of los. an output mask ( los_in hibit ) holds the output to the los pin high after power - on reset until the configuration register load from eeprom or microcontroller is complete. this avoids multiple transitions on the los pin during initialization, which can cause fault conditions to occur at the system level. transmitter signal path [contro l register address range a4h: 9eh to a1h ] the input to the transmitter signal path supports cml, lvpecl, hstl , and sstl electrical signalling schemes with a minimum of external components. the input may be either dc or ac coupled. an external 100? resistor provides differential terminati on. the internal potential dividers set the common mode level at 2.0v when the input is ac - coupled. figure 5 . tx_in and ben input termination and signal conditioning l o s _ r a w l o s d e b o u n c e t i m e o u t p e r i o d r e c e i v e d s i g n a l i n c r o s s e s a s s e r t t h r e s h o l d c r o s s e s d e a s s e r t t h r e s h o l d 5 0 u s t y p i c a l t x _ i n + t x _ i n - 0 v v d d i / p i n t e r f a c e 2 4 k 5 k 1 0 0 r 5 k 1 6 k a c c o u p l e d m o d e o n l y 0 v v d d 1 6 k 2 4 k
maxim integrated 14 the laser modulation current is controlled by the tx_moddac register with a resolution of 375 a per lsb (nominally). this register may be set by the host, or alternatively s et the mod lut_en bit to cause the tx_mod dac register to be automatically refreshed from the modulation lookup tab le (lut) every 10 ms . the modulation lut is stored in external eeprom at twi slave address a6h, register address range 80h to ffh. it is indexed using the upper 7 bits of temperature_uncal . if the modramp_en register is set then the value in tx_moddac ramps progressively from t he old valu e to the new value by 1 lsb every cycle of the internal 64mhz clock . this prevents glitches from occurring in the dac. if ramping is disabled then updates to tx_moddac are effective immediately. the modulation current is switched off between bur sts and when the laser safety system asserts a shutdown. burst_invert is used to invert the differential signal on ben . tx_invert is used to invert the polarity of the transmit signal path. eye optimiz ation the pulse width of the transmitted signal is adj usted by moving the crossing point of the eye up or down using tx_pwadjust_dir . use the tx_pwadjust_size to control the amount of adjustment, in the direction set by tx_pwadjust_dir . at maximum adjustment, the zero crossing point (a) is moved by 40% of the 0 - pk eye opening (b). the tx_pwadjust_hires register can be used to halve the adjustment step size and thus increase resolution (at the expense of halving the range). figure 6 . crossing point adjustment the tx_snubber register is used to snub out overshoot or undershoot in the output eye. tx signal detect [contro l register address range a4h: adh to aeh, beh to bfh ] the tx signal detect feature comprises two related areas of functionality: for external signal and rogue onu fault detect by the host, the MAX24001 controls the tx_sd pin as follows: tx_sd = '1' when there is light; tx_sd = '0' when there is no light from the laser. for on - chip "rogue onu fault detect", the MAX24001 detects the presence of light during the burst gap. this fault condition is input to the laser safety system which can then optionally shut down the laser within 100s of light being detected. figure 7 . tx_sd pin signal generation d i f f e r e n t i a l s i g n a l i s b a l a n c e d ( t x _ p w a d j u s t _ s i z e = 0 0 0 ) 0 v a b z e r o c r o s s i n g p o i n t m o v e d u p w i d t h o f z e r o p u l s e s d e c r e a s e s ( t x _ p w a d j u s t _ d i r = 0 ) z e r o c r o s s i n g p o i n t m o v e d d o w n w i d t h o f z e r o p u l s e s i n c r e a s e s ( t x _ p w a d j u s t _ d i r = 1 ) t x _ s d / t x _ f a u l t t x _ s h u t d o w n m p d b e n r o g u e o n u f a u l t d e t e c t l a s e r s a f e t y s y s t e m 1 0 t x _ s d c o n t r o l t x _ f a u l t c u r r e n t t h r e s h o l d
maxim integrated 15 the mp d current is compared with a threshold current set by the txsd_threshold register. this determines the mpd current level at which both tx_sd and rogue onu are detected. when ben = 0 the tx_sd l ogic transfers the comparato r output directly through to tx_ sd . in addition, t he rogue onu fault detect logic transfers the comparator output through to the laser safety system. the txsd_rogueonu_delay register specifies the delay (in cycles of the internal 64mhz clock) between the falling edge of ben and testing f or rogue onu. the rogue_onu_ fault condition is not generated during this time. when ben = 1 the tx_sd l ogic output goes high when the input from the comparator goes high. this state is latched. the tx_sd signal will then remain high until either the end of the burst, or until the comparator output remains low for a period of time exceeding the time defined by the txsd_deglitch_period register. this prevents tx_sd from toggling during a burst due to the pattern s ensitivity of the mpd current. ( during bias loop fast - start, tx_sd is held at 1 ) selection between tx_sd and tx_fault functionality is governed by the txsd_select register. the txsd_allow register holds the pin high until the configuration register load from eeprom (or microcontroller) is complete. this avoids multiple transitions on the tx_sd pin during initialization.
maxim integrated 16 rogue onu behavio r figure 8 . rogue onu timing tx_sd behavio r figure 9 . tx signal detect timing during the gaps the tx_sd logic is transparent and the comparator output is routed directly through to the tx_sd pin. during the bursts: (a) the tx_sd pin is asserted high when the mpd current first exceeds the threshold. (b) the tx_sd pin will not toggle in response to short term fluctuations of the mpd current above and below the threshold (due to the pattern sensitivity of the mpd current). (c) there is a requirement that the tx_sd pin responds within 50ns of the assertion o f ben. the mpd current is settled and the tx_sd circuitry can respond well within 50ns of the start of a burst. however, the MAX24001 will assert tx_sd high whenever a signal is detected during a long burst even if the signal does not appear until well aft er the initial 50ns. (d) if the laser stops outputting light during a burst , then there is a delay before tx_sd goes low. this is necessary in order to distinguish between the mpd current dipping below threshold due to a run of zeros, and the mpd current d ropping below threshold due to a legitimate loss of signal. the delay is programmable using txsd_deglitch_period . (e) if the signal is restored during a burst then tx_sd is asserted high again. b e n m p d i c o m p a r a t o r t h r e s h o l d t x _ s d c o m p a r a t o r o u t p u t b e n m p d i ( a ) t x _ s d ( b ) ( c ) ( d ) ( e ) > 5 0 n s
maxim integrated 17 laser biasing [contro l register address r ange a4h: a2h to a9h ] the bias current is controlled by the tx_biasdac register in one of six operating modes: operating mode description tx_biasmode <2:0> open loop, static tx_biasdac only changes when it is written by the host 000 open loop, lut tx_biasdac is constantly refreshed from values read from a temperature indexed lookup table (the bias lut) 001 closed loop, natural start an automatic power control (apc) loop constantly adjusts tx_biasdac in order to maintain a target laser output power level. tx_biasdac de faults to near - zero after power - up and then converges naturally on the target level over a duration of time dictated by the loop bandwidth. 100 closed loop, lut start the apc loop controls tx_biasdac , and tx_biasdac is prelo aded from the bias lut at power - up. 101 closed loop, fast start the apc loop controls tx_biasdac , and a fast - star t algorithm is invoked at power - up to rapidly converge the loop on the target power level. 110 closed loop, lut fast start the apc loop controls tx_biasdac . tx_biasdac is preloaded from the bias lut at power up, and then a fast - start algorithm is invoked to rapidly converge the loop on the target power level. 111 operational overview the tx_biasmode<2:0> register is a grouping of three individual controls registers: tx_biasmode<0> : bias_lut_enable tx_biasmode<1> : faststart_enable tx_biasmode<2> : apc_enable open - loop o peration clear the apc_enable register for open - loop operation. the l aser bias current is controlled by the tx_bias dac register with a resolution of 92.5 a per lsb (nominal). this register may be set by the host, or alternatively set the bias_lut_enable bit to cause the tx_biasdac register to be automatically refreshed from the bias lookup tab le (lut) every 10 ms . the bias lut is stored in external eeprom at twi slave address a6h, register address range 00h to 7fh. it is indexed using the upper 7 bits of temperature_uncal . i f the bi asramp_en register is set then the value in tx_biasdac ramps progressively from the old value to the new by 1 lsb every cycle of the internal 64mhz clock . this prevents glitches from occurring in the dac. if ramping is disabled then updates to tx_biasdac a re effective immediately.
maxim integrated 18 closed - loop o peration set the apc_enable register for closed - loop operation. the automatic power control (apc) loop compares a value of laser output power produced by the power m onitoring circuits with a target level set by tx _apc_target . this proportional error value is scaled using the apc_loop_gain and is then used to adjust the value of tx_biasdac (which has a number of internal precision extension bits). the apc_loop_gain register thus controls the bandwidth of the apc loo p. since the bandwidth of the loop is not very high, it is desirable to set the tx_biasdac register to a point as close as possible to the target laser power level before the apc loop takes over. this is achieved by pre loading the tx_biasdac register with a value from the bias lut and/or running a search algorithm (referred to as fast - start). these actions are both triggered by the bias_lut_enable and faststart_enable bits. when these bits are set, then a table lookup or fast - start will occur at the next available opportunity. once the lookup or fast - start has occurred then the se bits are cleared. the host may therefore re - trigger f ast/lut start by resetting bias_lut_enable and faststart_enable at any time. the bits are also set automatically as follows: o n power - up: tx_biasmode is configured from eeprom during sleep: the value in faststart_after_sleep is transferred to faststart_enable the value in bias_lut_after_sleep is tran sferred to bias_lut_enable during tx_disable: the value in faststart_after_txdisable is transferred to faststart_enable the value in bias_lut_after_txdisable is transferred to bias_lut_enable thus, the required lo op behavio r when the laser is enabled can be independently configured for reset, sleep mode and tx disable. this is further illustrated in the figure below: figure 10 . behavio r of the tx_biasmode register in closed - loop mode a p c _ e n a b l e f a s t s t a r t _ e n a b l e b i a s _ l u t _ e n a b l e 0 0 0 1 1 1 1 1 0 1 0 0 p o w e r - o n r e s e t i n i t i a l i s e f r o m e e p r o m l o a d t x _ b i a s d a c f r o m b i a s l u t f a s t s t a r t a l g o r i t h m i s e x e c u t e d i n i t i a l i s i n g n o r m a l o p e r a t i o n l a s e r e n a b l e d 1 1 1 1 1 f a s t s t a r t _ a f t e r _ s l e e p b i a s _ l u t _ a f t e r _ s l e e p s l e e p 1 1 0 1 0 0 n o r m a l o p e r a t i o n f a s t s t a r t a l g o r i t h m i s e x e c u t e d b i a s m o d e r e g i s t e r r e - l o a d e d d i s a b l e d b i a s m o d e r e g i s t e r r e - l o a d e d 1 1 0 1 0 0 f a s t s t a r t a l g o r i t h m i s e x e c u t e d n o r m a l o p e r a t i o n l o a d t x _ b i a s d a c f r o m b i a s l u t 1 0 f a s t s t a r t _ a f t e r _ t x _ d i s a b l e b i a s _ l u t _ a f t e r _ t x _ d i s a b l e
maxim integrated 19 fast - s tart algorithm [contro l register address range a4h: aah to ach ] figure 11 . fast - s tart algorithm timing during fast - start, the MAX24001 is temporarily re configured. the modulation driver sinks a constant current of i mod /2 on tx_out to represent the contribution made by the signal current to the average power. the power monitoring circuit is re configured to supply a direct comparison between the received mpd current and the target m pd current. the process of making a change to bias current and then a subsequent comparison of mpd current and target current is referred to as iteration . an iteration has a fixed duration (nominally 62 ns). initially, t he bias current is stepped up on eve ry iteration until the mpd current exceeds the threshold. the initial bias current step size a is ideally ? the modulation current, the rationale being that this is the largest step which can be taken whilst ensuring that the p1 power level is not exceeded . more generally, the initia l step size is defined as a = ( tx_ fstart_initial /256) x i mod . when the target level is exceeded the step size then decays (c). halving the step size every iteration amounts to a binary search. in practice , incomplete settling of the loop can result in a small overshoot of the target current level. it is therefore recommended that each step is slightly more than 0.5x the previous step. this is configurable using the fstart_decay register. the fstart_decay register determines th e multiplication factor applied to the step size on each subsequent iteration of the fast start algorithm. fstart_decay step decay multiplier 100000 100001 100010 100011 100100 100101 .. 101110 101111 32/64 = 0.5 33/64 = 0.516 34/64 = 0.531 35/64 = 0.547 36/64 = 0.563 37/64 = 0.5785 .. 46/64 = 0.719 47/64 = 0.734 the direction of each current step depends on whether the measured mpd current is above or below the target level. the number of iterations b is controlled by the fstart_duration registe r. the maximum number of iterations which can be guaranteed to complete within 3 x 400ns bursts is 15. a b c t a r g e t m p d c u r r e n t d m p d c u r r e n t ( l a s e r o u t p u t p o w e r ) b i a s c u r r e n t s t e p s i z e
maxim integrated 20 at the end of the fast - start algorithm, the laser output sta ge switches from sinking dc i mon /2 on tx_out to full amplitude signal. this may result in a brief c urrent spike. a facility is provided to optionally shut down the modulation current through the laser during this transition period (d). use the fstart_recovery_en and fstart_recovery_time registers to shut down the modulation current for 0, 1 or 2 iterati ons. apc loop b andwidth the apc_loop_gain register adjusts the gain of the apc control loop. loop bandwidth is calculated as a function of apc_loop_gain : where: mondac_lsb = 0.78 a biasdac_lsb = 92.5 a f clock = 64 mhz (typical) k mpd = 0.0625 when mpd_range = 10 0.25 when mpd_range = 01 1 when mpd_range = 00 apc_loop_gain gain 0000 0001 0010 : 1100 1101 1110 1111 2 - 15 2 - 14 2 - 13 : 2 - 3 2 - 2 2 - 1 1 power m onitoring a power monitoring circuit generates a digital measure of mpd current (laser power) based on time - averaged samples taken during bursts when the laser is enabled. it has three settings in order to accomm odate the wide range of monitor photodiode currents. t he range setting ( mpd_ range ) is chosen at the time that the module is calibrated, and does not change during normal operation of the apc loop. the unfiltered, 8 - bit digital measure of mpd current is used internally by the apc loop. mpd_range pd mirror gain i mon operating range ( a) 00 01 10 1 1/4 1/16 40 to 200 100 to 800 400 to 2000 tracking error in the tosa means that the mpd current may vary over temperatur e in a non linear way for a given laser optical power. if the temper ature - indexed tracking error lookup table (lut) is enabled then the digital measure of mpd current is multiplied by the values read from the lut. each entry in the lut represents a number in the range 0.5 (00h) to 1.5 (ffh), and 80h represents unity gain. b a n d w i d t h = 2 * k * k * ( b i a s d a c _ l s b * 4 ) * f a p c _ l o o p _ g a i n - 1 5 e l e c m p d c l o c k 2 * * 1 6 * m o n d a c _ l s b = 2 * k * k * 3 . 0 2 x 1 0 a p c _ l o o p _ g a i n - 1 5 e l e c m p d 6
maxim integrated 21 set the trackinglut_en bit to enable this feature. a correction factor is retrieved from the tracking error lut every 10 ms. this lut is stored in external eeprom at twi slave address a8h, register address range 80h to ffh. it is indexed using the upper 7 bits of temperature_uncal . the digital measure of mpd current (including tracking error compensation) is used by the apc loop to control bias current. power r eporting for power reporting purposes, the power monitor output is low - pass filtered to suppress t he pattern sensitivity of the mpd current. this filter bandwidth is programmable using the mon_bandwidth register. bandwidth = 64/ (2 x 2 (15 - n) ) where n is the 4 - bit integer mon_bandwidth value up to a maximum of 14. the filtered measure of laser power ca n be read from the txpower_uncal register. mon_bandwidth bandwidth at f clock = 64mhz 0000 0001 .. 1000 .. 1110 1111 311 hz 622 hz .. 80k hz .. 5.1 mhz no filtering the mpd_range should be set at a level which accommodates the expected range of mpd current. the MAX24001 is not designed to automatically range switch during normal apc loop operation. however, if the apc loop fails and the power monitor saturates then the mpd_range w ill temporarily switch so that power reporting can cover the full 0 to 2ma range of photodiode current. the range then recovers back to the original setting if the power monitor value drops back below 64. power leveling the power _levelling register implements gpon power leve l ling. set to 00, 01 , or 1x to reduce the modulation amplitude set by tx_moddac by x1, x0.5 and x0.25 , respectively. this register will also reduce the power level by having the same effect on the output of the tx_apc_ta rget register. power levelling does not affect the bias current in open - loop mode. laser safety [control r egist er address r ange a4h: afh to b3h ] the laser safety system generates two signals, tx_fault _int and tx_shutdown _int . tx_fault _int is pure status . it reports via both register and tx_fault pin whether one or more enabled fault conditions have occurred. the tx_fault pin can be configured to appear at pin 21 or 39 using pin_config0 . t x_shutdown _int is a control signal. it disables the bias and modula tion currents to the laser when one or more enabled fault conditions have occurred. fault conditions the fault conditions which affect tx_fault _int and tx_shutdown _int are: bias fault apc fault vref fault vdd fault tx disable fault soft tx fault rogueonu fault this occurs when the bias pin is shorted to ground . this occurs when the mpd pin is shorted to ground . this occurs when the rref pin is shorted to ground . this occurs when brownouts are detected on tx or txo . is given by: (tx_disable xor tx_disable_invert ) or soft_tx_disable where tx_disable is the pin value and soft_tx_disable is in sff - 8472 status_control . this occurs when the soft_tx_fault bit in software_faults regis ter is set. if the laser is on during a gap between bursts then this fault condition is generated.
maxim integrated 22 when the laser is in shutdown then the bias f ault condition is ignored by the laser safety system. when tx_shutdown is deasserted there is a 250s delay before the bias f ault condition is used. this allows the circuit which detect a ground short on the bi as pin time to settle before the bias f ault condition is seen by the laser safety system. architecture figure 12 . laser safety system the laser safety system (tx fault) generates the tx_ fault _int signal. the status of this signal can be accessed in the sff - 8472 status_control register. the signal is also multiplexed onto the tx_fault/tx_sd pin. every safety cell has its own pair of latch enable and fault enable control register bits. the fault co ndition can only propagate through to the output when _faulten = 1. when _latchen = 1 a latched version of the fault condition is used. the latch is held in reset when latching is disabled or when the tx_disable_fault signal is asserted. note that tx_d isable_fault is also a fault condition signal. when it is asserted, the laser_inhibit signal holds all latches in reset and forces the tx_fault_int signal to 1 . note that after the power - on reset , laser_inhibit is enabled . during initialization pin _con fig is the last configuration reg ister to be loaded from eeprom and therefore has the effect of clearing laser_inhibit and thus enabling the laser. ls_fault_status reports the status of the fault conditions at the inputs to the safety cells. the laser safe ty system is fully replicated for controlling laser shutdown. the system uses the ls_shutdown_faulten and ls_shutdown_latchen registers and produces the tx_shutdow n_int signal for disabling the modulation and bias currents . the internal architecture is otherwise the same a s the system for tx fault. the shutdown register can be found in hardware_status . the module tx supply (v cc_tx ) can be used in some applications to shut down the laser. this is supported in MAX24001 by detecting the removal of v cc_tx o n the v dd_txo pin. v cc_tx is connected to v dd_txo as shown in f igure alarm fault this occurs when one or more of the sff - 8472 ddm alarm flags are set to 1. the ls_ alarmflag_en . s o f t _ t x _ f a u l t t x _ d i s a b l e _ f a u l t s q r r e s e t 0 1 l a t c h e n a b l e f a u l t e n a b l e l s _ t x f a u l t _ f a u l t e n < 0 > l s _ t x f a u l t _ l a t c h e n < 0 > l a s e r _ i n h i b i t c e l l < 0 > t x _ d i s a b l e _ f a u l t b i a s _ f a u l t v d d _ f a u l t v r e f _ f a u l t a p c _ f a u l t a l a r m _ f a u l t r o g u e _ o n u _ f a u l t t x _ f a u l t _ p i n t x _ f a u l t _ i n t f a u l t c o n d i t i o n s s a f e t y c e l l s c e l l < 1 > c e l l < 2 > c e l l < 3 > c e l l < 4 > c e l l < 5 > c e l l < 6 > c e l l < 7 > t x _ s h u t d o w n _ i n t l a s e r s a f e t y s y s t e m ( t x f a u l t ) l a s e r _ i n h i b i t l a s e r s a f e t y s y s t e m ( t x s h u t d o w n ) l s _ s h u t d o w n _ f a u l t e n l s _ s h u t d o w n _ l a t c h e n s h u t d o w n
maxim integrated 23 13 . a shutdown is then asserted if the voltage falls below 2.7v. if the connection between v cc_tx and v dd_txo is not used , v dd_txo must be connected to another supply. figure 13 . v dd_txo configured to assert laser shutdown temperature sensor [control r egist er address r ange a4h: b 6h, b9 h , c1h ] the MAX24001 includes an integrated temperature sensor that reports the module temperature at the sensor transist or. the temp_ext_sensor register selects between an internal transistor or an external pnp transistor connected to the tsense and tsense_ret pins. if an external transistor is used then the pcb tracks connecting an external pnp transistor to the chip each have resistance << 1 ? . i.e. the tracks must be kept as short as possible. the temperature sensor reports a value in temperature_uncal once every 65ms. resolution is approximately 0.8c per lsb of temperature_uncal . part - to - part accuracy is optimized by adju sting temp_calibrate until each part reports the same value of temperature_uncal at a common temperature. setting leave_pu and tempsense_pu enables the temp erature sensor to be in a power - saving mode by powering down between reads. apd controller [contro l regis ter address range a4h: 94h ] figure 14 . apd biasing application figure 14 shows a simplified arrangement for controlling the apd bias voltage, whereby the fet is switched by a pulse width modulated signal. the duty cycle can be used to control the voltage across the capacitor. this voltage can be sampled at the tap point of the potential divider. the MAX24001 provides functions which support this approach. v c c _ t x / v d d _ t x o c o n n e c t i o n v c c _ r x v c c _ t x t r a n s c e i v e r i c v d d _ d i g 2 . 7 v v d d d e t e c t v d d _ r x v d d _ r x o v d d _ t x v d d _ t x o l a s e r s a f e t y a p d _ c t r l 3 . 3 v a d c r s s i
maxim integrated 24 figure 15 . apd biasing control loop components the pwm frequency can be configured to be 250 k hz, 500 k hz, 1mhz or 2mhz by pwm_frequency . the 8 - bit value of rx_apdpwm adjusts the dut y cycle from 0/256 to 255/256. high_v adjusts the drive level to 1.2v or 3.3v. the apd controller adjusts the value of rx_apdpwm according to the proportional and integral gain setting of the loop in registers k_proportional and k_integral such that the voltage level sampled on the adc pin converges on the target value rx_apd_target . the target value apdlut_en may be fixed, or it may be actively refreshed from the te mperature indexed apd lookup t able (lut) when target_lut_enable is set. this lut is stored in eeprom at two - wire slave address a8h, register address range 00h to 7fh. the lut is indexed by temperature_uncal . when the apd controller is active, a limit may be imposed on the maximum pwm duty using max_d uty . apd controller additional features apd safety features are also implemented. if the sampled value of rssi current exceeds rx_apd_i_threshold , or the sampled voltage on the adc pin exceeds rx_apd_v_threshold then the apc_ctrl pin driver is disabled (h i - z). set the thresholds to ffh to disable this feature. the apd controller is disabled when k _proportional and k _integral are both zero. the value in rx_apdpwm can be written directly, or will be periodically refreshed from the apd lut if pwm_lut_enable is set. the polarity of the output on apd_ctrl can be inverted by setting pwm_invert to 1. if an external control loop is used (for example, using an external dc - dc converter) then this loop could be controlled by the dac pin. the dac is controlled from the rx_apddac register. this will be periodically refreshed from the apd lut if dac_lut_enable is set. in this arrangement, the apd_ctrl pin can be used to control the shutdown input pin of the dc - dc converter. d igital diagnostics data generation [control r egist er address r ange a4h: b4h to b5h, e6h to eah ] temperature, s upply v oltage, l as er bias current, t ransmit power , and r eceived po wer are all periodically sampled. temperature the uncalibrated temperature can be read from the temperature_uncal register. a p d _ c t r l a d c p w m s i g n a l g e n e r a t o r a p d l u t a d c r s s i a p d f a u l t d e t e c t 1 v 2 d e f a u l t 1 c u r r e n t v o l t a g e r x _ a p d _ t a r g e t p w m p i c o n t r o l l e r
maxim integrated 25 supply voltage select between tx and rx supply voltages using adc_supplysel , and adjust the sampling rate using supply_bandwidth . the uncalibrated supply voltage can be read from the supply_uncal register. tx bias current the b ias c urrent measu red during a burst will continue to be reported between bursts, irrespective of the length of the gap. if the laser is deliberately shutdown by the laser safety system or by asserti ng tx_disable then bias current reports zero and the low alarm/ warni ng flag s are set. the uncalibrated bias current is read from the bias_uncal register. tx power the tx power measured during a burst will continue to be reported between bursts, irrespective of the length of the gap. if the laser is deliberately shutdown by the la ser safety system or by asserti ng tx_disable then tx power reports zero and the low alarm/ warni ng flags are set. the uncalibrated tx power is read from the txpower_uncal register. rx power the rssi pin can both source and sink a current ( rx_rssi_sink ) whic h is proportional to the optical power incident on the receiver. resolution can be enhanced by applying additional gain (x1, x1.5 or x2) to the current at the rssi pin using the rx_rssi_scale register (see los_rssi_config ). for rx power mea surement , the adc is used in non linear 3 - slope mode. this provides both wide dynamic range and high resolution at low powers. the uncalibrated, 3 - slope encoded value of rx power is read from the rxpower_uncal register. rssi current range ( a) rxpower_uncal gain x1 gain x1.5 gain x2 0 to 16 16 to 208 208 to 1232 0 to 11 11 to 139 139 to 821 0 to 8 8 to 104 104 to 616 0 to 32 3 2 to 128 128 to 255 adjust the rx power sampling bandwidth using rxpower_bandwidth .
maxim integrated 26 digital diagnostic monitors the raw digital measures of: temperature, supply voltage, bias current, tx power , and rx power are converted into calibrated sff - 8472 digital diagnostic monitor (ddm) values once every 10ms when sff_en is set and the main loop is active (mainloop_en is set). these registe rs are located in main_config. the following calibration constants are used: metric reference slope (sla : a4h) offset (sla : a4h) ddm (sla : a2h) temperature supply voltage tx bias current tx power rx power temp vcc bias txpower rxpower 00h C 01h 04h C 05h 08h C 09h 0ch C 0dh 10h C 11h (slope 0) 14h C 15h (slope 1) 02h C 03h 06h C 07h 0ah C 0bh 0eh C 0fh 12h C 13h (offset 0) 16h C 17h (offset 1) 60h C 61h 62h C 63h 64h C 65h 66h C 67h 68h C 69h all slope values (including rx p ower) are stored as 16 - bit fixed point (unsigned) as per sff - 8472 external calibration constants. the slope is calculated as ddm lsb s per adc increment, e. g. for supply voltage the slope unit (bit 8) represents units of 100 a per adc increment (hence the >>8 operation after multiplication). all offset values (i ncluding rx p ower) are stored as 16 - bit fixed point (signed two s complement) as per sff - 8472 external calibration constants. in all cases, the upper byte of the 16 - bit word is stored at the lower address. rx power has an additional pair of constants to support a rough piecewise linear approximation of the non linear characteristic of received optical power vs . rssi current. this occurs when a series resistor is used between the apd and the apd bias voltage g eneration circuit. it provides a form of compression, protecting the apd by reducing avalanche gain if current gets too high. temperature figure 16 . calculating the temperature ddm supply voltage figure 17 . calculating the supply voltage ddm t e m p e r a t u r e t e m p e r a t u r e _ u n c a l + x a 2 : 6 0 h C 6 1 h t e m p _ o f f s e t t e m p _ s l o p e 8 1 6 c a l i b r a t e d s f f - 8 4 7 2 d d m a / w l o o k u p > > 8 v c c s u p p l y _ u n c a l + x a 2 : 6 2 h C 6 3 h v c c _ o f f s e t v c c _ s l o p e 8 1 6 c a l i b r a t e d s f f - 8 4 7 2 d d m a / w l o o k u p > > 8
maxim integrated 27 tx bias current figure 18 . calculating the bias current ddm tx power figure 19 . calculating the t x power ddm the power monitor generates an 8 - bit measure of mpd current after a gain of 1, 1/4 , or 1/16 has b een applied . re - ranging increases the tx power value when gains < 1 have been applied to the mpd current. txpower_reranged = txpower_uncal << 4 when mpd_gain = 00 else txpower_uncal << 2 when mpd_gain = 01 else txpower_uncal rx power figure 20 . calculating the rx power ddm the following formulae are used to convert the 3 - slope rxpower_uncal value into a linear pseudo 12 - bit (0 to 2448) value: 0 < rxpower_uncal 32 linearized_rx_power = rxpower_uncal 32 rxpower_uncal 128 linearized_rx_power = ((rxpower_uncal C 32) * 4) + 32 128 rxpower_uncal 255 linearized_rx_power = ((rxpower_uncal C 128) *16) + 416 t x b i a s b i a s _ u n c a l + x a 2 : 6 4 h C 6 5 h b i a s _ o f f s e t b i a s _ s l o p e 8 1 6 c a l i b r a t e d s f f - 8 4 7 2 d d m a / w l o o k u p > > 8 t x p o w e r t x p o w e r _ r e r a n g e d + x a 2 : 6 6 h C 6 7 h t x p o w e r _ o f f s e t t x p o w e r _ s l o p e m p d _ r a n g e r e - r a n g e 8 1 2 1 6 c a l i b r a t e d s f f - 8 4 7 2 d d m a / w l o o k u p > > 8 t x p o w e r _ u n c a l r x p o w e r r x p o w e r _ u n c a l + x a 2 : 6 8 h C 6 9 h r x p o w e r _ o f f s e t r x p o w e r _ s l o p e l i n e a r i s e 8 1 2 1 6 c a l i b r a t e d s f f - 8 4 7 2 d d m a / w l o o k u p > > 8
maxim integrated 28 the selected pair of slope and of fset values depend on the value of linearized_rx_power . if linearized_rx_power is greater than rxpower_threshold , then use the slope and offs et pair from the address range 14h to 17h. otherwise use the slope and offset pair from address range 10h to 13h. thi s coarsely accommodates the non linearity of the curve of received optical power vs. rssi current. alarm and warning flags figure 21 . using 8 - bit c alibrated data to look up alarm and warning f lags figure 22 . alarm and warning lut mapping the uncalibrated 8 - bit diagnostic data values are used to index the alarm and warning luts. construct a lut by identifying the required threshold levels in absolute units (v, c, ma, w) and then reverse the calculations shown by the figures in the previous section to yield corresponding uncalibrated threshold levels. for tx and rx power , these should incorporate the range and 3 - slope encoding , respectively. a / w l u t 1 t e m p s u p p l y a / w l u t 2 b i a s t x p o w e r a / w l u t 3 r x p o w e r u n u s e d a l a r m h i g h a l a r m l o w w a r n i n g h i g h w a r n i n g l o w 7 6 5 4 3 2 1 0 a l a r m h i g h a l a r m l o w w a r n i n g h i g h w a r n i n g l o w a l a r m h i g h a l a r m l o w w a r n i n g h i g h w a r n i n g l o w 7 6 5 4 3 2 1 0 a l a r m h i g h a l a r m l o w w a r n i n g h i g h w a r n i n g l o w a l a r m h i g h a l a r m l o w w a r n i n g h i g h w a r n i n g l o w 7 6 5 4 3 2 1 0 u n u s e d 1 1 1 0 0 0 0 0 0 0 : : 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 : : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 : : 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 : : 0 0 1 1 1 1 1 1 0 0 h f f h l o w a l a r m t h r e s h o l d h i g h a l a r m t h r e s h o l d h i g h w a r n i n g t h r e s h o l d l o w w a r n i n g t h r e s h o l d a l a r m h i g h a l a r m l o w w a r n i n g h i g h w a r n i n g l o w t a b l e i n d e x e d u s i n g u n c a l i b r a t e d d a t a
maxim integrated 29 the ls_alarmflag_en register controls which of the ddm alarm flags contribute to the laser safety ala rm_fault fault condition. power - u p and sleep mode [control r egist er address r ange a4h: 8ch, b8h] the MAX24001 can be put into a low - power mode of operation when the sleep pin is asserted. this is achieved by combining t he sleep function with the chip - power sequencing, sleep can be configured to independently affect the rx and tx signal paths. rx signal path: the response to the sleep pin is controlled by the rx_respond_to_sleep pin register. tx signal path: the response to the sleep pin is controlle d by the tx_respond_to_sleep pin register. figure 23 . conditions for moving in and out of sleep mode t he device will only move betw een these states when power sequencing is enabled ( tx_powerup_en and r x_powerup_en are set ) . the host can alternatively put the MAX24001 to sleep using the tx_force_sleep and rx_force_sleep registers. o n s l e e p p i n a s s e r t e d a n d r e s p o n d i n g t o s l e e p p i n r e d u c e d p o w e r s l e e p p i n n o t a s s e r t e d o r ( s l e e p p i n a s s e r t e d a n d n o t r e s p o n d i n g t o s l e e p p i n )
maxim integrated 30 initiali z ation and control overview the MAX24001 is normally used in conjunction with a 2k byte eeprom. figure 24 . address map normal o peration during initializ ation, data is transferred from eeprom areas with twi slave addresses a0h and a2h into shadow areas of memory on the MAX24001 . device configuration data is transferred from area a4h into MAX24001 registers. du ring normal operation , the MAX24001 has exclusive access to the lookup tables held in eeprom using the twi master interface. the MAX24001 twi slave interface only decodes slave addresses a0h and a2h, and when the host accesses these areas it is accessing t he shadowed memory on the MAX24001 . the diagnostic data in the memory is regularly refreshed. using a m icrocontroller if the initializ ation fails , then the MAX24001 defaults to a state whereby the tx and rx paths are not enabled, the main loop is off, and all memory areas are accessible. a microcontroller may then upload data to registers and control the operation of the MAX24001 . module s etup to access eeprom (cf i nitialisation_status and system _control registers) ? c lear mainloop_en . this stops the main loop. ? w ait until eeprom_dma_idle is set. accesses to eeprom have then ceased. ? s et external_access to direct accesses via the twi slave interface to eeprom. all regi ons of the eeprom may then be accessed as long as the chip is in security level 2. access control [control regist er address range a2h: 7ch to 7fh, and a4h: 82h to 8 b h ] s f p m s a s e r i a l i d r e s e r v e d s f f 8 0 7 9 0 f f h a 0 h d i a g n o s t . ( e x t e r n a l c a l ) u s e r e e p r o m a 2 h a p d l u t a 4 h m o d u l a t i o n l u t a 6 h a 8 h a / w l u t 1 a / w l u t 2 a / w l u t 3 a a h a c h a e h b i a s l u t t r a c k i n g l u t u p p e r l o w e r e e p r o m m a x 2 4 0 0 1 m e m o r y a r e a s m a x 2 4 0 0 1 r e g i s t e r s m a x 2 4 0 0 1 c o n f i g / c o n t r o l m a x 2 4 0 0 1 ( i n t e r n a l c a l ) m e m o r y m e m o r y
maxim integrated 31 three levels of security are defined. the security level determines which areas of eeprom and register space may be accessed via the two - wire interface. the security level is selected by the password_entry register and can be read from the security_level r egister in system_status . level2 C ( password_entry value matches password2 ). the host has full read and write access to all address spaces. (password2 has priority over password1) . level1 C ( password_entry value matches password1 ). the host has read and write access to a0h and a2h only, as defined by the upper nibbles of the password_configa0 and password_configa2 registers. level0 C ( password_entry value matches neither password1 nor password2 ). the host has read and write access to a0h and a2h only, as defined by the lower nibbles of the password_configa0 and password_configa2 registers. password1 and password2 can only be written in level2. the security level will not change when writing a new value to password2 . typically access in level 0 is more re strictive than access in level1. read and write access to a2h:78h to 7fh is always permitted. if access is denied then the transaction is discarded in the case of a write, and returns ffh in the case of a read. during burst - mode accesses, access permission and destination are tested on a byte - by - byte basis.
maxim integrated 32 initializ ation sequence [control regist er addresses a4h: 80h, 81h, 8ch, e0h ] figure 25. initialization sequence the data integrity bytes are the first two bytes to be read from eeprom (addresses a4: 80h to 81h). if data_integrity0 = c3h and data_integrity1 = 5ah then it is inferred that the eeprom is co rrectly programmed and initializ ation continues. if the read acc ess fails (no eeprom) then eeprom_unresponsive is set. if the read access succeeds but the data integrity values are incorrect then eeprom_data_invalid is set. in both cases the transfer from eeprom is aborted to prevent MAX24001 defaults from being overw ritten with random data. the tx and rx paths will not power up and the MAX24001 will remain in the wait state at the start of the main loop. the d ata integrity values only exist in eeprom. they have no corresponding registers. t r a n s f e r r e m a i n i n g d a t a f r o m e e p r o m t o r e g i s t e r s a n d o n - c h i p m e m o r y : r e g i s t e r d a t a : a 4 : 9 0 h C b f h c a l c o n s t a n t s : a 4 : 0 0 h C 1 7 h s e r i a l i d : a 0 : 0 0 h C f f h d i g i t a l d i a g : a 2 : 0 0 h - 7 7 h a 2 : 8 0 h - f f h p o r t r a n s f e r d a t a f r o m e e p r o m t o r e g i s t e r s a 4 : 8 0 h C 8 f h d u r i n g t h i s t i m e t h e t w i s l a v e i n t e r f a c e i s d i s a b l e d . i f t h e t r a n s f e r f a i l s t h e n t h e e e p r o m _ u n r e s p o n s i v e r e g i s t e r b i t i s s e t i f t h e c o n t e n t o f t h e d a t a _ i n t e g r i t y r e g i s t e r s i s i n v a l i d t h e n t h e e e p r o m _ d a t a _ i n v a l i d r e g i s t e r b i t i s s e t w a i t u n t i l : t x _ p o w e r u p _ e n = t x _ p o w e r u p _ d o n e . a n d r x _ p o w e r u p _ e n = r x _ p o w e r u p _ d o n e c o n d i t i o n a l l y p o w e r u p t h e t x a n d r x p a t h s . o k ? y n w a i t f o r 1 0 m s . r e s e t t i m e r . o k i f e e p r o m _ u n r e s p o n s i v e = 0 a n d e e p r o m _ d a t a _ i n v a l i d = 0 m a i n l o o p
maxim integrated 33 main operating l oop [control regist er address a4h: b7h ] figure 25 . main operating loop the modulation, bias, apd , and tracking error luts are all 128 bytes and indexed by the upper 7 bits of the uncalibrated temperature sensor output ( temperature_uncal ). typically, lut entry 14h corresponds with a temperature of - 40 c. lut resolution is then 1.6 c between consecutive table entries. these values are approximate and may vary slightly from batch to batch. w a i t f o r 1 0 m s t i m e r t o e x p i r e . r e s e t t i m e r m o d u l a t i o n l o o k - u p t r a c k i n g e r r o r l o o k u p b i a s l o o k - u p a p d l o o k - u p c o n d i t i o n a l C o n l y d o t h i s i f m o d l u t _ e n = 1 c o n d i t i o n a l C o n l y d o t h i s i f b i a s l u t _ e n = 1 c o n d i t i o n a l C o n l y d o t h i s i f a p d l u t _ e n = 1 c o n d i t i o n a l C o n l y d o t h i s i f t r a c k i n g l u t _ e n = 1 t r i g g e r s f f - 8 4 7 2 c a l i b r a t i o n o n f i r s t p a s s , c l e a r l a s e r _ i n h i b i t a l l l o o k u p s p e r f o r m e d b e f o r e l a s e r i s e n a b l e d c o n d i t i o n a l C o n l y d o t h i s i f s f f _ e n = 1 m a i n l o o p _ e n = 1 ? y n a l a r m / w a r n l o o k - u p c o n d i t i o n a l C o n l y d o t h i s i f s f f _ e n = 1 m a i n l o o p
maxim integrated 34 two - wire interface (twi) prot ocol the sda_slave and scl_slave pin s are referred to as the slave two - w ir e i nterface (slave twi). the slave twi provides external access to both registers within the MAX24001 and to any device connected to the scl_master and sda_master pins (the master tw i). typically, an eeprom is connected to the master twi. framing and data transfer the two - wire interface comprises a clock line (scl) and a data line (sda). an individ ual transaction is framed by a start condition and a stop condition. a start condition occurs when a bus master pulls sda low while scl is high. a stop condition occurs when the bus master allows sda to transition low - to - high when scl is high. within the frame the master has exclusive control of the bus. the MAX24001 supports r epeated start conditions whereby the master may simultaneously end one frame and start another without releasing the bus by replacing the stop condition with a start condition. within a frame the state of sda only changes when scl is low. a data bit is transferred on a low - to - high transition of scl. data is arranged in packets of 9 bits. the first 8 bits represent data to be transferred (most significant bit first). the last bit is an acknowledge bit. the recipient of the data holds sda low during the ninth clock cycle o f a data packet to acknowledge (ack) the byte. leaving sda to be pulled high on the ninth bit signals a not - acknowledged (nack) condition. the interpretation of the acknowledge bit by the sender depends on the type of transaction and the nature of the byte being received. sda is bidirectional so that the master may send data bytes during write transactions and the slave may send data bytes during reads. device addressing the first byte to be se nt after a start condition is a slave address byte. the first seven bits of the byte contain the target slave address ( msb first). the eighth bit indicates the transaction type C 0 = write, 1 = read. each slave interface on the bus is assigned a 7 - bit slave address. if no slave matches th e address broadcast by the master then sda will be left to be pulled high during the acknowledge bit and the master receives a nack. the master must then assert a stop condition. if a slave identifies the address then it acknowledges it by pulling sda low. the master then proceeds with the transaction identified by the type bit. the two - wi re interface of the MAX24001 decode s slave address es a0 h to afh . figure 26 . address decoding example write transaction figure 2 8 shows an example of a write transaction. the address byte is successfully acknowledged by the slave, and the type bit is set low to signify a write transaction. after the first acknowledge the master sends a single data byte. all signalling is controlled by the master except for the sda line during the acknowledge bits. during the acknowledge cycle the direction of the sda line is reversed and the slave pulls sda low to return a 0 (ack) to the master. m s b 7 5 6 4 3 2 1 0 l s b s t a r t a c k s t o p r / w a d d r e s s s d a s c l
maxim integrated 35 figure 27 . write transaction the MAX24001 interprets the first data byte as a register a ddress. this is used to set an internal memory pointer. subsequent data bytes within the same transaction will then be written to the memory location addressed by t he pointer. the poin ter is auto incremented after each byte. there is no limit to the number of bytes which may be written in a single burst to the i nternal registers of the MAX24001 . read transaction figure 28 . read transaction figure 2 9 shows an example of a 2 - byte read transaction. the slave address byte is successfully acknowledged by the slave, and the type bit is set high to signify a read. after the ack the slave returns a byte from the location identified by the internal memory pointer. thi s pointer is then auto - incremented. the slave then releases sda so that the master can ack the byte. if the slave receives an ack then it will send another byte. the master identifies the last byte by sending a nack to the slave. the master then issues a s top to terminate the transaction. thus, to implement a random access read transaction, a write must first be issued by the master containing a slave address byte and a single data byte (the register address) as shown in figure 2 8 . this sets up the memory pointer. a read is then sent to retrieve data from this address (see figure 2 9 ). 7 1 s t a r t a c k s t o p s d a s c l 4 3 2 1 0 w 7 6 5 m s b a c k s d a d i r e c t i o n t o s l a v e f r o m s l a v e 7 1 s t a r t a c k s t o p s d a s c l r n a c k s d a d i r e c t i o n t o s l a v e f r o m s l a v e 7 0 7 0 a c k
maxim integrated 36 register descriptions for registers containing a single 8 - bit field, the msb of the field is stored in bit 7 of the register byte. note that reserved register bits are specified as read only. these registers should not be changed from their power - on reset (po r) default settings. register types are: r bit is read only via the s lave twi. writing to this bit will have no effect. the value may be changed by the MAX24001 to communicate operating status to the host. r/w bit is readable and writable via the slave twi. the value will not be changed by the device itself except under a device reset. e event bit. this bit is set to 1 by the when a specified event occurs. it is only cleared to 0 when the host writes 1 to it via the slave twi. writing a zero to this register has no effect. this bit is slave a ddress: a2h 6eh status_control status and control information (cf. sff - 8472 specification) bit field name type po r description 7 tx_disable_state r/w 0 state of the tx_disable pin 6 soft_tx_disable r/w 0 1: d isable the laser 5 4 p_down_status r state of the sleep pin 3 p_down_control r/w 0 1 : a ssert sleep 2 tx_fault_state r state of the tx_fault pin 1 rx_los_state r state of the los/sd pin 0 data_ready_bar r 1 changes to 0 when the transceiver is powered up and data is ready 7ah system_status additional vendor specific status made available to the user irrespective of security level. bit field name type po r description 7 6 rogue_onu e 0 1 : r ogue_onu condition is detected 5 excessive_bias r 0 1 : b ias dac exceeds tx_ bias_threshold 4 eeprom_dma_idle r 0 1 : eeprom is idle and may be accessed 3 eeprom_data_invalid r 0 1 : data integri ty check failed during initializ ation 2 eeprom_unresponsive r 0 1 : eeprom failed to ack the slave address during initiali z ation 1 C 0 security_level r 10 00h = level0, 01h = level1, 10h = level2
maxim integrated 37 7bh system_control additional vendor specific control bits made available to the user irrespective of security level. bit field name type por description 7 C 6 u ndefined 5 - 4 power_levelling r/w 00 gpon power lev elling: 00: x1, 01: x0.5, 1 x : x0.25 3 soft_rate_select r/w 0 0: ratesel0 control rx filter, 1: ratesel1 controls rx filter 2 tx_force_sleep r/w 0 1: f orce tx system into low - power sleep mode (if respond_to_sleep pin set) 1 rx_force_sleep r/w 0 1: f orce rx system into low - power sleep mode 0 external_access r/w 0 host access routing: 1: eeprom, 0: internal registers/memory 7ch password_entry0 r/w 00h write to this register to select the security level . l evel 2 if password_entry = password2 else .. l evel 1 if password_entry = password1 else l evel 0 7dh password_entry1 r/w 00h 7eh password_entry2 r/w 00h 7fh password_entry3 r/w 00h slave address: a4h 82h password1_0 r/w 00h holds the security level 1 password . 83h password1_1 r/w 00h 84h password1_2 r/w 00h 85h password1_3 r/w 00h 86h password2_0 r/w 00h holds the security level 2 password 87h password2_1 r/w 00h 88h password2_2 r/w 00h 89h password2_3 r/w 00h 8ah password_configa0 enables the access to the upper and lower halves of the a0h address space to be configured for security levels 0 and 1. bit field name type por description 7 level1_write_upper r/w 1 1: w rite access to upper half of a0h permitted in security level 1 6 level1_read_upper r/w 1 1: r ead access to upper half of a0h permitted in security level 1 5 level1_write_lower r/w 1 1 : w rite access to lower half of a0h permitted in security level 1 4 level1_read_lower r/w 1 1 : r ead access to lower half of a0h permitted in security level 1 3 level0_write_upper r/w 0 1 : w rite access to upper half of a0h permitted in security level 0 2 level0_read_upper r/w 0 1 : r ead access to upper half of a0h permitted in security level 0 1 level0_write_lower r/w 0 1 : w rite access to lower half of a0h permitted in security level 0 0 level0_read_lower r/w 1 1 : r ead access to lower half of a0h permitted in security level 0
maxim integrated 38 8bh password_configa2 enables the access to the upper and lower halves of the a2h address space to be configured for security levels 0 and 1. bit field name type por description 7 level1_write_upper r/w 1 1: w rite access to upper half of a2h permitted in security level 1 6 level1_read_upper r/w 1 1: r ead access to upper half of a2h permitted in security level 1 5 level1_write_lower r/w 1 1: w rite access to lower half of a2h permitted in security level 1 4 level1_read_lower r/w 1 1: re ad access to lower half of a2h permitted in security level 1 3 level0_write_upper r/w 0 1: w rite access to upper half of a2h permitted in security level 0 2 level0_read_upper r/w 0 1 : r ead access to upper half of a2h permitted in security level 0 1 level0_write_lower r/w 0 1 : w rite access to lower half of a2h permitted in security level 0 0 level0_read_lower r/w 1 1 : r ead access to lower half of a2h permitted in security level 0 8ch initialization_config early stage chip configuration at the start of the initialisation process. bit field name type por description 7 u ndefined 6 r/w 0 r eserved 5 tx_powerup_en r/w 0 1 : e nable automatic power - up sequencing for the tx s ystem 4 rx_powerup_en r/w 0 1 : e nable automatic power - up sequencing for the rx s ystem 3 C 0 r/w 0111 r eserved 90h rx_input configures the input buffer of the receive path and sets the receiver bandwidth. bit field name type por description 7 C C soft_rate_select . 1 C bit field name type por description 7 los_squelch = 0) C
maxim integrated 39 93h rx_driver controls the output amplitude and pre emphasis on rx_out bit field name type por description 7 C C C p - p 1111 : 88 0mv p - p step size is 45 mv 94h rx_apd_control configuration of the apd system and specifically the apd_ctrl and dac outputs. bit field name type por description 7 C rx_apd_target register periodically from the apd lut 1 pwm_lut_enable r/w 0 1 : l oad the rx_apdpwm register periodically from the apd lut 0 dac_lut_enable r/w 0 1 : l oad the rx_apddac register periodically from the apd lut 95h rx_apd_pi gain values for apd proportional - integral controller bit field name type por description 7 C C rx_apdpwm lsb s/ lsb of error value). 0 : 0 4 : 2 - 5 1 : 2 - 8 5 : 2 - 4 2 : 2 - 7 6 : 2 - 3 3 : 2 - 6 7 : 2 - 2 the error value is the difference between the sampled apd voltage and the rx_apd_target value. eg. if k_integral = 6 and error value = +2 then the rx_apdpwm register will be incremented by 2 x 2 - 3 = 0.25. (note that the rx_apdpwm register is the integer part of a fixed point register with 8 additional bits of precision. ) 2 C rx_apdpwm lsb s / lsb of error value): 0: 0 4 : 2 3 1 : 2 0 5 : 2 4 2 : 2 1 6 : 2 5 3 : 2 2 7 : 2 6 96h rx_apd_v_threshold type por while the apd voltage exceeds this thresh old, apd_ctrl is three - stated. note that a threshold of ffh amounts to turning off this feature. r/w ffh
maxim integrated 40 97h rx_apd_i_threshold type por while the apd current exceeds this threshold, apd_ctrl is three - stated. note that a threshold of ffh amounts to turning off this feature. r/w ffh 98h rx_apddac type por sets the apd dac output current from 0 to 500 type por sets the pwm duty cycle in the range 0/256 to 255/256 r/w 00h 9ah rx_apd_target type por sets the target voltage of the apd controller. r/w 00h 9bh los_rssi_config sets the los deb ounce period and los polarity. this register also contains bits used to control current on rssi pin. bit field name type por description 7 C 000 = 0s s 001 = 16s 101 = 80 s 010 = 32s 110 = 96 s 011 = 48s 111 = 112 s C type por sets threshold at which los is asserted r/w 00h 9dh los_deassert type por sets threshold at which los is deasserted r/w ffh
maxim integrated 41 9eh tx_input configures the input circuitry of the transmit path. pulse width of the transmitted signal is adjusted by moving the crossing point of the eye up or down. bit field name type por description 7 burst_invert r/w 0 1: i nvert differential signal on ben 6 tx_invert r/w 0 1 : i nvert differential signal on tx_in 5 C bit field name type por description 7 modramp_en r/w 1 1 : dac ramps from old value to new, 0 : immediate step change 6 C C a1h tx_moddac type por sets the cml output current for the laser driver (modulation current) r/w 00h a2h tx_bias the mpd_gain register applies gain to the mpd current. it does not change during normal operation and therefore the range must be selected to accommodate all expected values of mpd current. bit field name type por description 7 C C bit field name type por description 7 faststart_after_sleep r/w 0 1 : t rigger the fast - start algorithm when emerging from sleep mode 6 bias_lut_after_sleep r/w 0 1 : d o single bias lut lookup when emerging from sleep mode 5 faststart_after_txdisable r/w 0 1 : t rigger the fast - start algorithm when tx_disable deasserted 4 bias_lut_after_txdisable r/w 0 1 : d o single bias lut lookup when tx_disable deasserted 3
maxim integrated 42 a4h tx_apc the apc delay register controls the delay between the deassertion of laser shutdown and the activation of the apc loop counter. the apc loop gain sets the gain (and thus the bandwidth) of the apc control loop. bit field name type por description 7 C C - 15 0001: 2 - 14 0010 : 2 - 13 : 1101 : 2 - 2 1110 : 2 - 1 1111 : 1 a5h tx_apc_target type por this is the mpd current target level for both the apc loop and the fast - start algorithm. r/w 00h a6h tx_biasdac0 type por bits 7 - 0 of the 10 - bit value which controls the bias current. the default is non - zero so that there is sufficient current for the loop fault detect circuits to operate correctly. r/w 28h a7h tx_biasdac1 bit field name type por description 7 C C type por if tx_biasdac <9 - 2> exceeds tx_bias_threshold then the excessive_bias bit is set in system status. r/w ffh a9h tx_mon_bandwidth determines the bandwidth of the first order digital low pass filter which is applied by the power monitoring circuit to the measured value of mpd current. bit field name type por description 7 C C type por determines the initial step size of the fast - start algorithm. r/w 80h
maxim integrated 43 t abh tx_fstart_decay determines the multiplication factor applied to the step size on each step of the fast - start algorithm after the mpd current first exceeds the target threshold. bit field name type por description 7 C C bit field name type por description 7 fstart_recovery_en r/w 1 1 : b riefly shut down bias and modulation after the fast - start algorithm 6 fstart_recovery_time r/w 0 0 : s hu t down for single iteration, 1: s hut down for 2 iterations 5 C bit field name type por description 7 C C type por the approximate time between the loss of transmitted signal and the deassertion of tx_sd during a burst: 00h : 16 ns to 31ns 01h : 31 ns to 62ns 02h : 46 ns to 92ns a: b to c b = (a + 1) x 15.625ns c = 2b r/w 02h
maxim integrated 44 afh ls_txfault_faulten enables the fault conditions associated with the tx_fault laser safety system bit field name type por description 7 a larm r/w 1 1: e nable this fault condition for the tx_fault laser safety system 6 rogue_onu r/w 1 1 : e nable this fault condition for the tx_fault laser safety system 5 soft_tx_fault r/w 1 1: e nable this fault condition for the tx_fault laser safety system 4 tx_disable r/w 0 1 : e nable this fault condition for the tx_fault laser safety system 3 v dd r/w 1 1 : e nable this fault condition for the tx_fault laser safety system 2 v ref r/w 1 1 : e nable this fault condition for the tx_fault laser safety system 1 a pc r/w 1 1 : e nable this fault condition for the tx_fault laser safety system 0 b ias r/w 1 1 : e nable this fault condition for the tx_fault laser safety system b0h ls_txfault_latchen latches the fault conditions associated with the tx_fault laser safety system bit field name type por description 7 a larm r/w 1 1: e nable latching for this fault condition 6 rogue_onu r/w 1 1 : e nable latching for this fault condition 5 soft_tx_fault r/w 0 1 : e nable latching for this fault condition 4 tx_disable r/w 0 1 : e nable latching for this fault condition 3 v dd r/w 1 1 : e nable latching for this fault condition 2 v ref r/w 1 1 : e nable latching for this fault condition 1 a pc r/w 1 1 : e nable latching for this fault condition 0 b ias r/w 1 1 : e nable latching for this fault condition b1h ls_shutdown_faulten enables the fault conditions associated with the shutdown laser safety system bit field name type por description 7 a larm r/w 1 1: e nable this fault condition for the shutdown laser safety system 6 rogue_onu r/w 1 1 : e nable this fault condition for the shutdown laser safety system 5 soft_tx_fault r/w 0 1 : e nable this fault condition for the shutdown laser safety system 4 tx_disable r/w 1 1 : e nable this fault condition for the shutdown laser safety system 3 v dd r/w 1 1 : e nable this fault condition for the shutdown laser safety system 2 v ref r/w 1 1 : e nable this fault condition for the shutdown laser safety system 1 a pc r/w 1 1 : e nable this fault condition for the shutdown laser safety system 0 b ias r/w 1 1 : e nable this fault condition for the shutdown laser safety system
maxim integrated 45 b2h ls_shutdown_latchen latches the fault condition s associated with the shutdown laser safety system bit field name type por description 7 a larm r/w 1 1: e nable latching for this fault condition 6 rogue_onu r/w 1 1 : e nable latching for this fault condition 5 soft_tx_fault r/w 0 1 : e nable latching for this fault condition 4 tx_disable r/w 0 1 : e nable latching for this fault condition 3 v dd r/w 1 1 : e nable latching for this fault condition 2 v ref r/w 1 1 : e nable latching for this fault condition 1 a pc r/w 1 1 : e nable latching for this fault condition 0 b ias r/w 1 1 : e nable latching for this fault condition b3h ls_alarmflag_en controls which of the ddm alarm flags contribute to the laser safety alarm_fault fault condition. bit field name type por description 7 temp_hifault_en r/w 0 1 : a larm fault occurs when temp exceeds high temp threshold 6 temp_lofault_en r/w 0 1 : a larm fault occurs when temp below low temp threshold 5 supply_hifault_en r/w 0 1 : a larm fault occurs when supply exceeds high supply threshold 4 supply_lofault_en r/w 0 1 : a larm fault occurs when supply below low supply threshold 3 bias_hifault_en r/w 0 1 : a larm fault occurs when bias exceeds high bias threshold 2 bias_lofault_en r/w 0 1 : a larm fault occurs when bias below low bias threshold 1 txpower_hifault_en r/w 0 1 : a larm fault occurs when txpower exceeds high txpower threshold 0 txpower_lofault_en r/w 0 1 : a larm fault occurs when txpower below low txpower threshold b4h adc_filter the samples of supply and rxpower may be low pass filtered using a filter with programmable bandwidth. 00 : fs/(2 x pi x 64) = 0.25hz 01 : fs/(2 x pi x 32) = 0.5hz 10 : fs/(2 x pi x 16) = 1hz 11 : fs/(2 x pi x 8) = 2hz fs = 100hz based on measurements every 10ms. bit field name type por description 7 C C C C bit field name type por description 7 C C dd_tx 10 : v dd_rx 01 : v dd_txo 11 : v dd_rxo 3 C
maxim integrated 46 b6h temp_config configures the temperature sensor bit field name type por description 7 temp_ext_sensor r/w 0 1 : u se external sensor, 0 : u se internal sensor 6 r/w 11 r eserved 5 leave_pu r/w 1 0: e nable tempsense_pu 4 C 0 u ndefined b7h main_config selects the operations performed when the main loop is enabled. operations are performed once per iteration of the loop. bit field name type por description 7 biaslut_en r/w 1 1 : l oad tx_biasdac register form the bias lut 6 sff_en r/w 1 1 : r ecalculate sff - 8472 ddms 5 rx_apddac , rx_apdpwm or rx_apd_target register from the apd lut 2 modlut_en r/w 1 1 : l oad the tx_moddac register from the modulation lut 1 bit field name type por description 7 C C bit field name type por description 7 C C type por the threshold that defines which pair of rx power calibration constants is used. if the 3 - slope encoded sample of rx power is above this threshold then select rxpower_slope1 and rxpower_offset1. otherwise select rxpower_slope0 and rxpower_offset0. r/w ffh
maxim integrated 47 beh pin_config0 pin function and polarity configuration bit field name type por description 7 bit field name type por description 7 - 4 bit field name type por description 7 C bit field name type por description 7 C C bit field name type por description 7
maxim integrated 48 e1h ls_fault_status reports real time status of fault conditions at input to the laser safety system bit field name type por description 7 a larm r been asserted. write 1 to these bits to clear back to 0 bit field name type por description 7 a larm e bit field name type por description 7 C type por the temperature sample value before calibration r
maxim integrated 49 e7h supply_uncal type por the supply sample value before calibration r type por the bias sample value before calibration r type por the tx_power value before re - ranging and calibration r type por the rxpower sample value before calibration r type por the uncalibrated measure of apd voltage r
maxim integrated 50 simplified interface models figure 29 . interface diagrams l o s , t x _ s d v d d v c c m p d v d d b i a s v d d 5 0 ? 5 0 ? r x _ i n + r x _ i n - v d d v c m 5 0 ? 5 0 ? v d d v d d r x _ o u t + r x _ o u t - t x _ o u t + / - t x _ i n + b e n + t x _ i n - b e n - v d d v d d 1 6 k ? v d d 2 4 k ? 5 k ? v d d 1 6 k ? v d d 2 4 k ? 5 k ?
maxim integrated 51 onu application diagrams figure 30 . lvpecl external terminations figure 31 . cml external terminations ? ? ? v c c 1 3 0 ? ? ? ? v c c 1 3 0 ? t x _ i n + b e n + t x _ i n - b e n - v d d v d d 1 6 k ? v d d 2 4 k ? 5 k ? v d d 1 6 k ? v d d 2 4 k ? 5 k ? m a x 2 4 0 0 1 1 0 0 ? v c c v c c 5 0 ? 5 0 ? t x _ i n + b e n + t x _ i n - b e n - v d d v d d 1 6 k ? v d d 2 4 k ? 5 k ? v d d 1 6 k ? v d d 2 4 k ? 5 k ? m a x 2 4 0 0 1
maxim integrated 52 p ackag e information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix charact er, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 40 tqfn - ep t4055+2 21 - 0140 90 - 0002
53 maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim inte grated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specificati ons without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. m a x i m i n t e g r a t e d , 1 6 0 r i o r o b l e s , s a n j o s e , c a 9 5 1 3 4 1 - 4 0 8 - 601 - 1 0 0 0 ? 2012 maxim integrated products, inc. the maxim logo and maxim integrated are trademarks of maxim integrated products, inc. revision history revision number revision date description pages changed 0 11 /1 2 initial release

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